Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

Matthias L. Vermeer, Raymond J.E. Hueting, Luca Pirro, Jan Hoentschel, Jurriaan Schmitz

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Abstract

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.
Original languageEnglish
Article number9305941
Pages (from-to)497-502
Number of pages6
JournalIEEE transactions on electron devices
Volume68
Issue number2
Early online date23 Dec 2020
DOIs
Publication statusPublished - 1 Feb 2021

Keywords

  • Capacitance
  • FinFETs
  • Ideality
  • Interface states
  • Logic gates
  • MOS transistors
  • Silicon
  • Silicon devices
  • Silicon on insulator
  • Silicon-on-insulator
  • Subthreshold
  • Transistors
  • Traps
  • silicon on insulator
  • traps.
  • interface states
  • silicon devices
  • subthreshold

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